1. Field of the Invention
The present invention relates to the field of dielectric materials, and more particularly, to the field of dielectric materials particularly suitable for use in the formation of multilayer conductor structures.
2. Background Information
A high density interconnect structure, methods of fabricating it and tools for fabricating it are disclosed in U.S. Pat. No. 4,783,695, entitled "Multichip Integrated Circuit Packaging Configuration and Method" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,835,704, entitled "Adaptive Lithography System to Provide High Density Interconnect" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,714,516, entitled "Method to Produce Via Holes in Polymer Dielectrics for Multiple Electronic Circuit Chip Packaging" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,780,177, entitled "Excimer Laser Patterning of a Novel Resist" by R. J. Wojnarowski et al.; U.S. patent application Ser. No. 249,927, filed Sept. 27, 1989, entitled "Method and Apparatus for Removing Components Bonded to a Substrate" by R. J. Wojnarowski, et al ; U.S. patent application Ser. No 310,149, filed Feb. 14, 1989, entitled "Laser Beam Scanning Method for Forming Via Holes in Polymer Materials" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 312,798, filed Feb. 21, 1989, entitled "High Density Interconnect Thermoplastic Die Attach Material and Solvent Die Attachment Processing" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 283,095, filed Dec. 12, 1988, entitled "Simplified Method for Repair of High Density Interconnect Circuits" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 305,314, filed Feb. 3, 1989, entitled "Fabrication Process and Integrated Circuit Test Structure" by H. S. Cole, et al.; U.S. patent application Ser. No. 250,010, filed Sept. 27, 1988, entitled "High Density Interconnect With High Volumetric Efficiency" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 329,478, filed Mar. 28, 1989, entitled "Die Attachment Method for Use in High Density Interconnected Assemblies" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 3,020,filed Oct. 4, 1988, entitled "Laser Interconnect Process" by H. S. Cole, et al.; U.S. patent application Ser. No. 230,654, filed Aug. 5, 1988, entitled "Method and Configuration for Testing Electronic Circuit and Integrated Circuit Chips Using a Removable Overlay Layer" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 233,965, filed Aug. 8, 1988, entitled "Direct Deposition of Metal Patterns for Use in Integrated Circuit Devices" by Y. S. Liu, et al.; U.S. patent application Ser. No. 237,638, filed Aug. 23, 1988, entitled "Method for Photopatterning Metallization Via UV Laser Ablation of the Activator" by Y. S. Liu, et al.; U.S. patent application Ser. No. 237,685, filed Aug. 25, 1988, entitled "Direct Writing of Refractory Metal Lines for Use in Integrated Circuit Devices" by Y. S. Liu, et al.; U.S. patent application Ser. No. 240,367, filed Aug. 30, 1988, entitled "Method and Apparatus for Packaging Integrated Circuit Chips Employing a Polymer Film Overlay Layer" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 342,153, filed Apr. 24, 1989, entitled "Method of Processing Siloxane-Polyimides for Electronic Packaging Applications" by H. S. Cole, et al.; U.S. patent application 289,944, filed Dec. 27, 1988, entitled "Selective Electrolytic Deposition on Conductive and Non-Conductive Conductive Substrates" by Y. S. Liu, et al.; U.S. patent application Ser. No. 312,536, filed Feb. 17, 1989, entitled "Method of Bonding a Thermoset Film to a Thermoplastic Material to Form a Bondable Laminate" by R. J. Wojnarowski; and U.S. patent application Ser. No. 363,646, filed Jun. 8, 1989, entitled "Integrated Circuit Packaging Configuration for Rapid Customized Design and Unique Test Capability" by C. W. Eichelberger, et al. Each of these Patents and Patent Applications is incorporated herein by reference. Each of the above patents is incorporated herein by reference.
Briefly, in this HDI system, integrated circuits or other electronic devices are attached to a substrate with their connection pads exposed. A dielectric layer of KAPTON.RTM. polyimide available from E. I. DuPont de Nemours is laminated over the electronic chips and substrate using, as a thermoplastic adhesive, a layer of ULTEM.RTM. polyetherimide resin available from General Electric Company, via holes are drilled in this composite dielectric layer in alignment with each connection pad to which it is desired to have the first layer of metallization of the HDI structure connect, the first metallization layer is deposited and patterned (if not deposited in a patterned manner) and further dielectric layers and metallization layers are applied over the initial metallization layer, if needed, until the structure is complete.
This structure places special requirements on the dielectric materials. In particular, in order for the final structure to be usable over a wide temperature range, the dielectric layers must have high melting points and high thermal stability. They must also be laser ablatable by ultraviolet light in order to form the via holes through which different layers of metallization are connected. In the HDI system, laser processing (ablation, photoresist exposure, etc.) is normally done with one, or at most, two passes of the laser beam with a power ranging from 0.5 to 2.0 watts with a preferred maximum power level being about 1.5 watts. Thus, when a dielectric layer is characterized as being laser ablatable, it means that such a layer can be totally removed by one or two passes of a laser beam of this power level and when it is characterized as not being laser ablatable, it means that a layer is not completely removed by one or two passes of such a laser beam.
To minimize the complexity and cost of equipment for fabricating such high density interconnect structures, it is considered desired to be able to do all laser processing at a single frequency in order that only a single laser is required. Accordingly, preferred materials are those which may be processed at a laser frequency of 351 nm. This frequency was selected in accordance with the characteristics of desirable dielectric layers such as Kapton.RTM. polyimide available from E. I. DuPont de Nemours and the fact that there are commercial photoresists which can be processed at this frequency. ULTEM.RTM. polyetherimide resin available from General Electric Company has been used as an adhesive layer in this high density interconnect structure for bonding Kapton.RTM. to the underlying structures. The ULTEM.RTM. resin is laser ablatable at 351 nm. The ULTEM.RTM. material has a melting point in the neighborhood of 217.degree. C. or higher, depending on its specific formulation. This ULTEM.RTM. high temperature adhesive layer is suitable for use in permanent structures.
In those metallization layers in which signal conductors (as opposed to ground or power plane layers) run, a significant portion of the area contacted by the next dielectric layer comprises the preceding dielectric layer on which that metallization layer is disposed.
One of the important features of this HDI structure is its repairability. This structure may be repaired by heating the structure to the melting or softening point of the thermoplastic ULTEM.RTM. resin layer which serves as the adhesive portion of the first dielectric layer. The entire HDI overlay structure may then be peeled off the substrate and the integrated circuit chips without damage to the chips or their connection pads. Thereafter, a defective chip may be removed and replaced. A new HDI overlay structure is then formed on the substrate and chips. In this manner, faulty chips may be replaced and errors such as unintentional shorts and open circuits in the HDI metallization structure may be repaired without damage to good electronic chips. This makes this HDI structure feasible for use with circuits including many expensive chips since a faulty chip or an error in circuit connection does not render the other, good chips in the structure unusable.
It is important for this repairability that the upper dielectric layers not bond to the metallization in the via holes of the first dielectric layer in a manner which results in tearing of contact pads on the chips during removal of the HDI overlay layer. Consequently, it is considered necessary to avoid the presence of thermoset materials in the via holes in the first dielectric layer. In this application, when we say "thermoplastic", we mean a material which when repeatedly heated and cooled, retains substantially the same softening temperature with the result that the layer may be heated in order to render it fluid and removable. When we say "thermoset", we mean a material which on reheating, remains solid at a substantially higher temperature than the temperature at which it was initially liquid or fluid. This change in softening temperature is generally a result of cross-linking within the polymer of which the layer is formed in a manner which creates a new structure having a substantially higher melting temperature or which no longer melts.
Thermoset materials which are thermoset at high temperatures such as 250.degree. C.-350.degree. C. are generally considered unsuitable for use in the HDI structure where an ULTEM.RTM. resin is used as the adhesive layer for the initial Kapton.RTM. layer because the ULTEM.RTM. softens at a temperature in the vicinity of 217.degree. C. (ULTEM.RTM. 1000) or 236.degree. C. (ULTEM.RTM. 6000). Further, since most such thermoset materials cross-link by condensation, unacceptable quantities of water become trapped within dielectric layers. This results in detrimental effects on the underlying electronic chips, on the included metallization and/or in undesirable effects upon heating above 100.degree. C. where the water vaporizes and causes separation of different dielectric layers.
Epoxies, although they cure by non-condensation reactions, have been considered unacceptable as the later dielectric layers because of their rigid, brittle nature which makes safe removal of HDI overlayers for repair difficult and because of generally poor adhesion between successive epoxy layers.
A problem which has been encountered in forming multilayer HDI structures is the tendency of thermoset materials to not adhere well to an underlying thermoset layer of the same material because of a lack of linking between the two layers as a result of the first layer having been fully cross-linked prior to application of the second layer. With thermoplastic materials, the solvents used for applying subsequent layers normally partially redissolve the preceding layers, thereby providing good adhesion, but often resulting in an attendant cracking or crazing of the layers as a result of uneven stresses. As has been set forth in some of the above-identified patents and applications, a siloxane polyimide available under the trade names SPI-129 and SPI-135 from Huls America, which is formulated with a diglyme solvent does not result in cracking and crazing of an underlying ULTEM.RTM. adhesive layer. This makes SPI-129 a suitable material as the dielectric layer which overlies the first dielectric layer and fills the via holes in the first dielectric layer since there are no adverse reactions between the SPI-129 and the underlying Kapton.RTM. and ULTEM.RTM. layers and because this is a thermoplastic material, having a softening point in the vicinity of 100.degree.-150.degree. C. Unfortunately, difficulty has been encountered in using the SPI-129 as the sole dielectric material for subsequent layers of the multilayer structure because of the tendency of the initial SPI-129 layers to soften during application of subsequent layers with a resulting shifting of the conductors disposed thereon in combination with solvent crazing effects.
Use of additional thermoset material/thermoplastic adhesive layer films (similar to the initial Kapton.RTM./ULTEM.RTM. dielectric layer) laminated over underlying HDI layers has been found to be unacceptable because of a tendency of the metallization in those underlayers to shift as a result of the lamination pressure used to bond the subsequent layer to the underlying layers.
While the high density interconnect (HDI) structure which is disclosed in the above-identified patents and applications may be fabricated with a single layer of metallization, there are many systems which are suitable for fabrication in the HDI structure which require multiple layers of metallization in order to properly interconnect all of the electronic components of the system. Consequently, there is a need for dielectric materials which may be processed to form multiple layers of dielectric interleaved with metallization layers in a manner which produces a reliable, high quality interconnect structure which is free of crazing, cracking and other visible problems in the dielectric material and metallization layers.
A number of materials and processes are available to the industry for providing dielectric layers in multilayer structures such as multilayer printed circuit boards. However, we have found that these materials are unsuitable for HDI use for a number of reasons. First, many require curing at greater than 250.degree. C. and preferably in excess of 350.degree. C. for from 1 to 3 hours in order for imidization to take place. Many of these materials suffer from shrinkage with the result that they apply undue stress on the substrate to which they are applied, and in many cases, can even warp silicon wafers into a cup having a depth of as much as 40 mils (0.102 mm) for a 4 inch (10.16 cm) diameter wafer. Further, if each layer is fully cured prior to application of the next layer, interlayer adhesion is poor and delamination often results. Attempts to process these materials without fully curing each layer before application of the next layer leads to cracking and crazing in the second or higher layers.
Solvent crazing is a recognized problem in forming multiple layers of a particular polymeric material. This is due, at least in part, to the solvent partially redissolving the upper surface of the preceding layer. Many processing steps carried out in the HDI process such as sputtering, reactive ion etching, ion milling and so forth, further sensitize the surfaces of such layers in a manner which aggravates the cracking and crazing problems. Other available materials are not laser drillable at 351 nm, provide too thin a dielectric layer or are processed at too high a temperature. A further problem is that amine cures are not acceptable in structures having aluminum metallization because of the adverse effects on that metallization. Epoxies, being thermoset materials, are difficult to use, while polyesters, acrylics and urethanes are unacceptable because of various failure modes and their general inability to remain stable at temperatures in excess of 125.degree. C.
While this discussion has focused on the General Electric Company's High Density Interconnect (HDI) structure, those skilled in the art will recognize that many of these same problems are present in the multilayer printed circuit board art. There are solutions to a number of these problems in the multilayer printed circuit board art. However, these solutions are inapplicable to the HDI structure because the printed circuit board art involves the use of temperatures which are high enough themselves or which are high enough in combination with the period of exposure that unacceptable degradation of components of the HDI structure would result. These components of the HDI structure may be the integrated circuits which are being interconnected thereby other materials used in the HDI structure. Still other printed circuit board solutions to these problems are inapplicable to HDI because they would render the HDI structure unrepairable.
There is a need for a dielectric composition and structure which allows multiple dielectric layers to be stacked without a tendency for the metallizations to shift, without a decrease in the maximum operating temperature of the structure and without cracking or crazing of any of the dielectric layers.